When designing computer systems which require high data rates, such as supercomputers developed by Cray Research, Inc., the assignee of the present invention, the design of the individual logic gates is of importance in optimizing the performance and speed of the system. The logic circuits must have high switching rates and short propagation delay times in order to increase the speed of the system. While maintaining a short propagation delay, the logic circuits must also be designed so that they do not consume a high amount of power which may generate excess heat and adversely affect the performance of the transistors. Also, among other design considerations, the logic circuits must have a minimum of components in order to increase the packing density and fit more logic gates onto a particular integrated circuit chip.
In attempting to increase the speed or clock rate of a system in order to achieve high data rates, the propagation delays within the components of the system are of primary importance. One must ensure that the propagation delays within the logic gates and drivers or other circuits are of short enough duration so that a signal within any part of the system has adequate time to reach its destination within a given clock cycle. One method of increasing the speed of a system, and thus the number of operations per second which may be performed, is by decreasing the propagation delays within the logic gates and the circuitry which drives the gates.
Emitter Coupled Logic (ECL) has typically been the logic used for high speed applications, since, in silicon (Si) technology, it has demonstrated the shortest propagation delay times. ECL achieves high switching rates and short propagation delays due to the non-saturating characteristics of the logic. By avoiding the saturation region, the transistors within the logic circuit do not accumulate as much charge and, consequently, the storage times are decreased. The switching of states in the ECL gate is accomplished by the current steering properties of a basic differential amplifier.
Motorola introduced Emitter Coupled Logic, known as MECL for Motorola's Emitter Coupled Logic, in 1962. Two popular versions of MECL with the short propagation delay times are MECL 10K and MECL 10KH, introduced in 1971 and 1981 respectively. A more recent version is MECL 100K, which is faster than MECL 10K and MECL 10KH and has a more stable transfer characteristic.
MECL 10K uses a basic differential amplifier, one side of which is electrically connected to a temperature and voltage bias network. The other half of the differential amplifier consists of bipolar junction transistors connected in parallel, the inputs of the gate applied to the bases of the transistors. The outputs of the gate are emitter followers connected to the collectors of the differential amplifier which provides for two outputs, the OR and NOR functions. The OR output is derived from the collector of the transistor connected to the bias network and the NOR output is taken from the node consisting of the collectors of the input transistors. The emitter follower outputs provide both level shifting so that the outputs are compatible with MECL 10K input levels and a low output impedance which is useful for a high fan-out capability or driving transmission lines.
The current steering properties of the differential amplifier provide the means for switching the state of the logic circuit without using the saturation region of the transistors. When the logic gate is in a particular state, nearly all of the current in the differential amplifier is driven through one side of the amplifier, and the transistor in that side operates in the active region. A change in the input voltage levels to the gate, which will switch the state of the logic gate, alters the voltage difference across the differential amplifier so that the transistor which had previously been in the active region turns off, and a transistor on the other side of the differential amplifier turns on. In this manner, current is diverted from one side of the differential amplifier to the other as the gate switches states. It is this type of current steering in the differential amplifier which changes the state and, therefore, the output voltage levels of the gate. Since the transistors in ECL gates do not enter the saturation region and accumulate excess charge, the transistors turn off faster than in logic which utilizes the saturation region for switching of states. The current in the differential amplifier, therefore, rapidly switches from one side of the amplifier to the other. This contributes to short propagation delay times. With decreased storage times, and fast turn off times of the transistors, as a result of the non-saturating properties of the logic, MECL 10K achieves a propagation delay of approximately 2 nanoseconds.
MECL 10KH is a slight variation of the MECL 10K logic gate. It contains a different bias network and, instead of using a resistor coupled to the emitters of the differential amplifier, it uses a transistor as a constant current source to the differential amplifier. With these changes, as well as advances in processing, the MECL 10KH logic gate has a propagation delay of approximately 1 nanosecond.
The reference voltage supplied by the voltage bias network to the differentially connected transistors is not completely independent of temperature in the MECL 10K and MECL 10KH gates. Changes in temperature can cause changes in both the reference voltage and the output voltage levels. Also, variations in the supply voltage can affect the reference voltage. MECL 100K gates have additional circuitry which provides for improvements over MECL 10K and MECL 10KH. The additional circuitry causes the MECL 100K gate to be almost completely independent of variations in temperature and supply voltage, which results in a very stable transfer characteristic. In addition to these improvements, MECL 100K is slightly faster than MECL 10KH, and it has a propagation delay of approximately 0.75 nanoseconds.
MECL logic gates are designed to drive transmission lines. The emitter followers provide a low output impedance and current sourcing capability required to drive a twisted pair line outside of the integrated circuit chip on which the MECL circuit resides.
Even though MECL has been the popular logic used in systems requiring high data rates, the speed of MECL is reaching its limits, based in part upon the limitations of Si technology. Also, due to its high power dissipation, MECL is difficult to implement in large-scale (LSI) integrated circuit packages.
One method of overcoming the limitations due to the physical characteristics of Si is the use of gallium arsenide (GaAs). The electron mobility is six to seven times greater in GaAs than in Si. The use of GaAs enables one to design logic gates with lower power without sacrificing speed.
The present invention introduces new logic families, one of which is Emitter Collector Dotted Logic (ECDL).
Another new logic family introduced by the present invention is Emitter Emitter Logic (EEL).
ECDL and EEL logic gates use fewer components than MECL gates which results in a higher packing density on the integrated circuit chip. Also, these new logic families improve upon the power dissipation and propagation delays of MECL.
EEL and ECDL make use of novel high speed transient and current switch drivers to drive signals between groups of logic gates and outside of an integrated circuit chip.
The present invention also introduces Source Drain Dotted Logic (SDDL), which is an implementation of ECDL with a transient driver in GaAs. This utilizes the favorable characteristics of GaAs for the production of logic gates with much lower power while maintaining the same speed.
Another new logic family introduced by the present invention is Source FET Logic (SFL), which uses enhancement mode and depletion mode GaAs MESFETs.